Processing devices such as computers, servers, mobile telephones, and storage devices typically incorporate one or more buses coupled between a processor and a memory. As is well known, the power consumption in a given such processing device can be heavily influenced by the number and frequency of signal transitions that occur on these buses. For example, in processing devices that include one or more processor core integrated circuits, such as field-programmable gate arrays (FPGAs) or custom application-specific integrated circuits (ASICs), both on-chip and off-chip bus transition activity can represent significant sources of power dissipation.
As one illustrative example of bus transition activity, consider an instruction address bus over which addresses change sequentially from 0 to 2″-1. On average, one can expect a significant number of transitions on a bus of this type. However, the number of transitions is even larger if the addresses instead change randomly between 0 and 2″-1, rather than sequentially from 0 to 2″-1.
Accordingly, a variety of techniques have been developed that attempt to reduce such bus transition activity in order to control the overall power consumption of the processing device. Such techniques include, for example, encoding algorithms such as bus invert algorithms, frequent value codes and self-organizing lists, all of which attempt to exploit weights or other statistical properties of individual samples to be transferred over the bus. The bus invert algorithms typically utilize the binary weight of a given sample to determine if that sample should instead be sent over the bus in complemented form in order to reduce transition activity. Encoding algorithms based on frequent value codes and self-organizing lists are generally configured to determine samples that appear on the bus repeatedly and map those samples to respective code words with lower transition activity.
These and other conventional techniques for reducing bus transition activity can be problematic. For example, although certain of the techniques mentioned above can produce acceptable results in the case of sequential execution, such techniques generally do not perform as well in the presence of particular types of program constructs such as loops, jumps or subroutine calls. Alternative techniques such as work zone encoding (WZE) and dynamic sector encoding (DSE) attempt to address these drawbacks, but unfortunately these techniques can significantly increase encoder and decoder complexity, leading to an undesirable increase in the power consumption of these processing device components, which is contrary to the goal of reducing overall device power consumption.